Accessing image stored in SDRAM sent through PCIex from Intel Atom host on DE2i-150

`timescale 1 ps / 1 ps

module test_use_manual_input_read_2(

//avalon master

avm_m0_address, // m0.address

avm_m0_byteenable_n,

avm_m0_chipselect,

avm_m0_read_n, // .read

avm_m0_waitrequest, // .waitrequest

avm_m0_readdata, // .readdata

avm_m0_readdatavalid,

//avm_m0_write_n, // .write

//avm_m0_writedata, // .writedata

clk, // clock.clk

reset, // reset.reset

seven_seg_out,

user_press_count_n,

user_press_start_n,

done,

avm_m0_state,

avalon_address,

seven_seg_out_2

);

//avalon master

output reg [31:0] avm_m0_address; // m0.address

output [3:0] avm_m0_byteenable_n;//4'b1111 means full 32bit

output avm_m0_chipselect;

output avm_m0_read_n; // .read

input avm_m0_waitrequest; // .waitrequest

input [31:0] avm_m0_readdata; // .readdata

input avm_m0_readdatavalid;

// output avm_m0_write_n; // .write

//output reg [31:0] avm_m0_writedata; // .writedata

output reg [31:0] seven_seg_out;

output [31:0] seven_seg_out_2;

input user_press_start_n;

input user_press_count_n;

output reg done;

reg [2:0] avm_m0_state;

output [2:0] avm_m0_state;

output [31:0] avalon_address;

input clk; // clock.clk

input reset; // reset.reset

parameter start_address = 32'h00000000;

parameter end_address = 32'h00000000+32'd1228800;

always@(posedge clk)

if(reset) begin

avm_m0_state<=0; done<=0;

end

else begin

case (avm_m0_state)

0: if(user_press_start_n)avm_m0_state <=0;

else begin avm_m0_state <=1;avm_m0_address<=start_address; end

1: if(avm_m0_waitrequest) avm_m0_state<=1;//request to read

else begin avm_m0_state<=2;end//start to read and flip

//2: if(avm_m0_readdatavalid) begin seven_seg_out<= avm_m0_readdata; avm_m0_state<=3;end

// else begin avm_m0_state<=2;end

2: begin seven_seg_out<= avm_m0_readdata; avm_m0_state<=3;end

3: if(user_press_count_n) avm_m0_state<=3;//request to write

else begin avm_m0_state<=4;end

4: if(!user_press_count_n) avm_m0_state<=4;//request to write

else begin avm_m0_state<=5; avm_m0_address<=avm_m0_address+32'h4;end

5: if(avm_m0_address==end_address) begin avm_m0_state<=0; done<=1; end

else avm_m0_state<=1;

endcase

end

assign avm_m0_byteenable_n = 4'b1111;

assign avm_m0_read_n = ~(avm_m0_state==1 || avm_m0_state==2);

assign avm_m0_chipselect = (avm_m0_state==1 || avm_m0_state==2);

assign avalon_address = avm_m0_address;

assign seven_seg_out_2= avm_m0_readdata;

endmodule

i have re-written the code

i use this code to make a custom qsys component (avalon master)

i am trying to accessing the sdram which has address 0x0800_0000 until 0xffff_ffff

i store my image into sdram at starting address address 0x0800_0000 until 0x0812_c000

does all master reads value from slave according to this diagram??

https://www.alteraforum.com/forum/attachment.php?attachmentid=8887

do i need to read "readdatavalid' value from slave when i perform "read from slave to master"???

i need help urgently

hope there is someone can help me

thankss