Forum Discussion
Hi End wei,
Yes, I plan to use fPll for transceiver. But now I only test the fPLL reset and it's reconfig. From the transceiver PHY user guide, I believe that the calibration will occur at POR & user-mode, and at user-mode, it will occure only after we send recalibration instruction to fPLL; But from the simualtion result and debug on board, I found that every time I set 0x1 to 0x2e0[1] (pll_powerdown through the avalon-memory mapped register), there is always once recalibration before pll locks. If this action right, when I can not provide suitable reference clock to fPLL, I can only write 0x1 to 0x2e0[1] to complete recalibration and reset fPLL, but from the debug on board, fPLL didn't work. and Only do I send one recalibrate instruction to fPLL, fPll will work. So I don't know the function of the recalibration which occurs after I reset fPLL.
Brs,
Lambert
Hi Lambert
Can you share your simulation results?
Thanks.
Eng Wei
- lambert_yu5 years ago
Contributor
Hi EngWei,
The attahced is the simulation result(once reset through control register), you will find that pll_cal_busy is asserted and pll_locked deasserted.
- EngWei_O_Intel5 years ago
Frequent Contributor
Hi Lambert
From your statement
"when I can not provide suitable reference clock to fPLL, I can only write 0x1 to 0x2e0[1] to complete recalibration and reset fPLL, but from the debug on board, fPLL didn't work. and Only do I send one recalibrate instruction to fPLL, fPll will work."
What do we mean by "fPLL didn't work" and "fPLL will work"? Do we mean the fPLL cannot get reset or cannot lock? The fPLL is not expected to work when you don't have a proper reference source.
From the waveform you shown, the behavior seems correct, where you have pll lock deasserted when issue a powerdown, and pll_cal_busy asserted when calibration is issued.
Thanks.
- EngWei_O_Intel4 years ago
Frequent Contributor
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Eng Wei