Forum Discussion
mario
New Contributor
New ContributorAbout the System PLL in Agilex 5
Regarding the System PLL in Agilex 5, the reference clock input can be supplied not only from the dedicated transceiver input pins but also from HVIO pins. However, when assigning the pins, the foll...
marioNew Contributor
New ContributorThank you.
I would like to confirm whether assigning the System PLL reference clock to an HVIO pin is considered not recommended.
According to the following user guide, it appears that supplying a reference clock from an HVIO pin is possible: https://docs.altera.com/viewer/book-attachment/7knH5a7~TA2WJGdpfH~dQA/dlqlFRJhjLOWTYNYgDTWiQ-7knH5a7~TA2WJGdpfH~dQA
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
Using the refclk pin from HVIO bank is definitely an accepted solution. However, there is a restriction as mentioned in the following document page:
Also, as the warning message suggests, the pin should be a clock pin which can be routed to global network.
Regards
