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mario's avatar
mario
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8 months ago

About the System PLL in Agilex 5

Regarding the System PLL in Agilex 5, the reference clock input can be supplied not only from the dedicated transceiver input pins but also from HVIO pins. However, when assigning the pins, the foll...
Transceiver
mario's avatar
mario
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3 months ago

Thank you.

I would like to confirm whether assigning the System PLL reference clock to an HVIO pin is considered not recommended.
According to the following user guide, it appears that supplying a reference clock from an HVIO pin is possible: https://docs.altera.com/viewer/book-attachment/7knH5a7~TA2WJGdpfH~dQA/dlqlFRJhjLOWTYNYgDTWiQ-7knH5a7~TA2WJGdpfH~dQA

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    I’d appreciate it if you could confirm whether the issue is now resolved.​

     

    Regards

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Dear Customer,

    I assume that your issue is resolved. As there are no further inquiries, I will step back and allow the community to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    Altera Technical Support