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Now I'm writing an interface between Avalon bus and a LSI, changing Avalon bus signals(read, write,ect) to LSI control signals. An interface can deal with burst transfer is preferred.
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Are you sure you need burst? Does the LSI interface use a start address followed by multiple data phases like a DDR, or can it just accept data on every cycle? If the latter is the case, then the Avalon components can post writes and prefetch reads on every clock cycle, so a burst interface is not required.
Can you post a part number for the LSI device. I'll take a look.
Cheers,
Dave
Honored Contributor
