About lane stable of simplex transceiver RX
Hi all,
I am facing one strange problem :
For current design with simplex transceiver rx using quartus prime 16.0 standard version, after compiling, I got the .pof file and download to FPGA board, the transceiver can work normally.
But for the same project, I updated to quartus prime 18.0 standard, and only update related IPs using auto update function, after compiling, I got the .pof file and download to FPGA board, the parallel data from some lanes among the simplex transceiver RX always have error.
I compared the fitter report between two verions:
I found that there is some warnings on 18.0 version compared to 16.0:
1) 18576 The transceiver with supply "VCCR_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V";
2) 18576 The transceiver with supply "VCCT_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V";
I do not know does it is one effect factor and I have no idea for this problem now.
Note: for version 18.0, there is only fewer time, I can get one good pof ( transceiver can work normally), most of times, the transceiver can not work well. And there's no timing problem and the FPGA board is good, the USRCLK and refclk is good, reset process follows the requirements.
FPGA : Arria 10 10GX115N2F45E1SG.
Could someone provide some advice for me, thanks.
Brs,
Lambert