A10 PCIe-SRIOV IP is not updating the shadow bus interface with MSI-X capability updated

Hi SK, The update is to the MSI-X enable field of message control Register of the MSI-X capability, written from the host (root port). When MSI-X enable/function mask fields of Message control register are updated, the PCIe-SRIOV HIP is expected to send these updates on the control shadow Interface of the IP, which is not happening. I have taken the snapshot of PCIe HIP signals from the simulation waveform dump, which I have shared already in the previous message. The snapshot indicates that the bit[2] of the ctl_shdw_cfg is changing (ctl_shdw_cfg[6:0] changes from 6’h1 -> 6’h5) with the write to MSI-X capability, which set the MSI-X enable field of MSI-C Message Control Register, but ctl_shdw_update is not asserted for this change. Thanks, RamaMohan