A10 PCIe SR-IOV supported tag + bandwidth

Hi PPham,

By referring to the newer version of document, I don't see the tag is 256 anymore. 32 or 64 should be the right one to support.

Here is the user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

Regarding to the bandwidth, It seem like the FPGA can't write data to host fast enough? You may increase the payload size, or longer burst mode. Beside, the host may not return credit back to HIP fast enough where need to improve the host processing capability.

Regards -SK

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