Honored ContributorIt seems the video demo examples on altera.com is not updated to v7.2. i took the 2D Fir 71 example and mimicked it using v7.2. it looks like the 72 vip stuff in dsp builder is easier to use than 71.
the video source i used is from matlab \MATLAB\R2007a\toolbox\vipblks\vipdemos
Honored ContributorNemo,
Nice job. Actually the only other thing I like is to use the AvST sink and source blocks for the IO. If you use those, then this model can be detected by SOPC Builder and automatically integrated as a component. The other cool thing about 7.2 is the IP isn't generated until you run quartus, which means its faster to try different IP settings. The design I attached can show you that (but I didn't include the video), there is also the same thing for AvMM components. BrianHonored ContributorYes, this will be helpful.
