New Contributor
Regular ContributorHi,
This IP has only one input clock, and this is the clock signal for all the register. The input sampling rate should be depending on the “in_valid” signal as well. Besides, the “in_ready “ signal is the output signal of the IP, a valid input data is required both “in_valid” and “in_ready” signals are asserted.
Please refer to figure 7 (timing diagram) in the user guide below, and see if there is any difference with your waveform.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_cic.pdf
Regards -SK
New ContributorDear SengKok,
Thank you very much for your reply! It turns out that my issue is indeed caused by timing and the in_valid signal and I have managed to solve the main problem. Now my CIC filter works under the same clock for the input signal and the noise disappears.
A minor problem is that the filter outputs a constant non-zero value when it is supposed to be zero. In my case, I set the output to 8 bits with Hogenauer Pruning, and the filter outputs signed decimal -48 when it is supposed to output zero. The screenshot of ModelSim's output is attached. In this case the output is supposed to attenuate down to 0. Also, the filter's output decreases when it is supposed to increase, while the shape of the output is correct. Do you know what could cause these problems?
