a problem in using the fifo

thank you Rysc, the name i typed two address yesterday is wrong, the two address is not wraddr and rdaddr, it is rdusedw and wrusedw. i used the fifo module. the verilog logic is as following:

fifo_receiver U1(

.aclr(fifo_aclr),

.data(fifo_data_in),

.rdclk(clk_out),

.rdreq(clk_out_en & rd),

.wrclk(clk_in),

.wrreq(write_fifo_8_req),

.q(data_out),

.rdempty(fifo_empty),

.rdusedw(fifo_8_rdusedw[9:0]),

.wrfull(fifo_full),

.wrusedw(fifo_8_wrusedw[9:0])

);

the wrclk and the rdclk are asynchronous. the wrclk is 100MHz clock in burst mode. the rdclk is a stable 27MHz clock. i.e.the fifo is read by a constant 27MHz clock, when the fifo is almost empty, the 100MHz write clock write some byte into the fifo, when the fifo is almost full, the write clock stops write.

normally, the wrusedw and rdusedw increase together in the writing period and decrease in the not-writing period.

the problem i met is sometimes the wrusedw and rdusedw always decrease in the writing period and Not-writing period. And sometimes the two address always increase. This makes the system work in the wrong condition.