A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi Ven Ting,

Sorry for late reply, I was bit busy with an another project. I would like to have your support to complete this project successfully.

1)In the sub-design (Counter_FIFO_SignalTap.zip), I have been setting avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1 using the button in the FPGA board.

2)"Can you the add clock signal that drives the source_data and fifo_o_out_readdata, and the signals that carry the data before passing it to the fifo_o_out_readdata signal in the Signal Tap to check that the correct data are passed to fifo_o_out_readdata?"

You mean I have to add th clock signal that drives the source_data and fifo_o_out_readdatain the SignalTap GUI window to view it? Then The signalTap should run in some different clock? I mean the default clock? (currently signal tap is running in the same clock as clock signal that drives the source_data and fifo_o_out_readdata .

3) "did you compile successfully on the original PCIe DMA transfer example design without adding Signal Tap?"

Yes I did

4)"There is a similar issue discussed in the Intel Community Forum."

In the thread you mentioned basically talks about some problem with connection while adding an IP to a design (so he can change it easily). But in our case we are adding Signal Tap to the design and the connections are done automatically, so may I know you are suggesting to go and change them manually?

Thank you and regards

Sijith