A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi,

Thank you very much for your reply. May I know that you are talking about the .qsys file from the attached ModifiedDesign.zip community.intel.com/t5/Programmable-Devices/Modifying-the-PCIe-DMA-transfer-example-design-for-Arria-10/m-p/1477669#M90418

or some other screenshot attachments?

Actually my modification is the first step of a couple of modification (a kind of step by step). After current step (testing the counter-FIFO writing to DDR4 and then DMA read data on DDR4 from a hostcomputer), I would like to replace the counter data with an input datastream that injected from external source through the QSFP+ port to FIFO(the input data rate is around 1.5 GB/s).

So involving the DMA controller to write data to DDR4 at this step, will help to efficiently handle the high speed input data (1.5 GHz/s in next step of my project ) writing to DDR4 and then DMA read from DDR4 by host computer (without any data loss), is that makes any sense for you? If not please let me know. Also, it would be great if you could give me any idea/suggestion that can help too.

sure I will try generating the EMIF example design as you suggested (could you please elaborate a bit how the EMIF example design will help us?)