A design based on the PCIe DMA transfer example design for Arria 10 device.

Yup the example design provided by Intel works fine (Even though I had some problem initially, It was a kind of random crashes. I assume its somehow related to the physical DDR4 memory element--when I re-insert the physical card the problem resolves)

The real issue is when I modify the design. When I added a FIFO + Counter to the design (I used Platform Designer for Integrating FIFO+ Counter IP to the DMA transfer example design), the test application (I removed the writing part from the test application retaining the read part) simply fails. Fails I mean I could read data but all of then are sum junk data. A screen capture of running the API application from the host computer is attached.

Platform designer view of the modified system (DMA transfer example + FIFO + Counter) : https://community.intel.com/t5/Programmable-Devices/How-to-read-data-from-the-DDR4-memory-of-a-Modified-PCIe-DMA/m-p/1468923#M90078 please go through the attached screenshot (PNG files) of my first message in the thread.