64B/66B encoding and decoding support for custom data

Hello CheePin,

Thanks for the confirmation. Are there any Intel FPGA IP cores which can be used for 64B/66B encoding outside the transceiver?

I would like to know whether I can use 10GBASE-R for any desired line rate or is it fixed to 10G only(Single channel without channel bonding). Note: The reason for asking this question is cause I have observed in the Intel® Arria® 10 Transceiver PHY User Guide that the architecture for 10GBASE-R shows fixed values of clocks and line rate with the line rate shown to be 10.3125 Gbps.

The required line rates for my application may come in the range of 12Gbps to 24Gbps on single channel. Will it be possible for me to implement this using 10GBASE-R without channel bonding?

Thanks and Regards,

Ron

Hello CheePin,

Thank you for the help.

Till now, what I have understood is that 64B/66B is supported only 10GBASE-R and supports line rate of only 10.3125Gbps. The 64B/66B encoding should be done by User Logic in case any other protocol is needed to be implemented.

Here are few queries I have regarding the configuration.

Ill use Intel Transceiver with following configurations

• Transceiver Configuration Rules : Basic (Enhanced PCS)
• Transceiver Mode: TX/RX Duplex
• Number of Channels: 1
• Data Rate: in the range of 12Gbps to 24Gbps

Enhanced PCS settings

• Enhanced PCS/PMA interface width: 64
• FPGA fabric/ Enhanced PCS interface width: 66
• Tx 64B/66B encoder: Disbaled
• Rx 64B/66B decoder: Disbaled

Note: I have mentioned the settings which looked necessary.

Let us assume the scenario, where I will be using the above configured transceiver and I will loopback the data.

Query 1: If I provide the 64bit data and 2 bit header, whether the transceiver will append the header to the data and create the 66bit serial data which will be transmitted on the differential line or will it do this only when 64B/66B encoding is enabled? ( I am under the impression that the header is only appended to the data when 64B/66B encoder is enabled, hence would like some clarification regarding this)

Query 2: If the above query holds good (Header will be appended to data even though the 64B/66B encoder is disabled) then whether the Transceiver Rx logic will decode the data properly ( provide the 2 bit header in the header bus and 64bit data in the data bus) and give it to the user? (Note: Raising this query with the assumption that if the Transceiver Tx can append header even when 64B/66B Encoder is disabled then the Transceiver Rx will be capable of removing the header from the serial data even though the 64B/66B Decoder is disabled)

Query 3: Whether the received data will be properly aligned always or is there a possibility for the decoded data to be misaligned?

For now these are the basic doubts I have regarding the Transceiver Functionality and would be glad if these could be cleared.

Thanks and Regards,

Ron