3g-sdi test pattern generator

Hi, everyone.

I have problem in using 3g-sdi test pattern generator.

I'm modifying the example code of sdi from Altera.

(the folder path is "C:\altera\11.1\ip\altera\sdi\example\a2gx_tr")

In this example code, the test pattern generator is implemented in several HDL files.

However, I would like to replace these HDL files with the test pattern generator in Altera VIP.

I've tried to generate a sd-sdi test pattern generator (720*480 interlaced) and a clocked video output in qsys and connect them to the sdi transmitter. This sd-sdi signal is connected back to sd-sdi receiver to check the rx_status. It works.

However, if I use a 3g-sdi test pattern generator (1920*1080 progressive) and a clocked video output. It doesn't work.

Does anyone know how to solve this problem?

Test pattern generator and clocked video output

wire tx_data;
wire tx_ln;
wire tx_trs;
// instance (3G)
tpg_cvo tpg_cvo_inst(
.clk_clk(clk_sdi_148_5),
.reset_reset_n(~reset),
.cvo_clocked_video_vid_clk(clk_sdi_148_5),
.cvo_clocked_video_vid_data(tx_data),
.cvo_clocked_video_underflow(),
.cvo_clocked_video_vid_trs(tx_trs),
.cvo_clocked_video_vid_ln(tx_ln)
);	

SDI transmitter

wire tx_std;
wire tx_gxb_tx_clkout;
// 
assign tx_std = 2'b10;
wire tx_pclk;
assign tx_pclk = tx_std? clk_sdi_148_5: (tx_std? clk_sdi_74_25: clk_sdi_27); 
// instance
sdi_tx sdi_tx_inst(
.rst_tx(1'b0),
.tx_pclk(tx_pclk),			
.tx_serial_refclk(clk_sdi_148_5),	// 148.5MHz
.txdata(tx_data),
.tx_trs(tx_trs),
.tx_ln({11'h000, tx_ln}),
.tx_std_select_hd_sdn(),
.enable_ln(1'b1),
.enable_crc(1'b1),
.tx_data_type_a_bn(1'b1),		// for 3G-SDI
.gxb4_cal_clk(gp_clk),			// 100Mhz, 10MHz ~ 125MHz as suggested
.sdi_reconfig_clk(clk_50),
.sdi_reconfig_togxb(reconfig_togxb),
.sdi_gxb_powerdown(1'b0),
.tx_std(tx_std),				
.sdi_tx(tx_p_o),
.tx_status(),
.gxb_tx_clkout(tx_gxb_tx_clkout),
.sdi_reconfig_fromgxb(reconfig_fromgxb)
);