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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

17044 error while running the analysis and synthesis in the design

Hi Team, i have created on qsys design which contains NIOS II processor + ddr3 + other ips+ custom logic in cyclone v gx device. with this i tried to compile the design in quartus 22.1 tool, i ...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Because in the BDF, there're connections made to the ddr3. Probably there're inappropriate connections to the ddr3 i/o. Does the error still occur if removing connections to the ddr3 in BDF? If no, probably this is related to ddr3 connection problem, may need to open a new thread with title target ddr3 to get related expert help.


Thanks,

Sheng


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    ok , maybe i will create another threat. Thanks!