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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

17044 error while running the analysis and synthesis in the design

Hi Team, i have created on qsys design which contains NIOS II processor + ddr3 + other ips+ custom logic in cyclone v gx device. with this i tried to compile the design in quartus 22.1 tool, i ...
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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

Hi ,

If the error is for Custom RTL , i can modify the io connection. But the error is throwing ddr3 ip library file connected in qsys. Even i tried one of the solution shared in intel forum that make qsys file as top file. And observed no error for qsys top file. But if i make bdf file as top, i am getting this error.