.qip and .sip generated files manually added to project . On compile entities in .qip not found. Before I start cutting and pasting modules into existing.v files, what's proper way to incorporate these PLLs? Details of transcript warnings below.

Hi Len, 1.Go to Processing -> start -> start testbench writer. 2.Check the meassge window : Info (201000): Generated Verilog Test Bench File C:/progm/plltop/simulation/modelsim/pll.vt for simulation 3.check the path & open the .vt file & copy the module name(like : pll_vlg_tst ) 4.Follow the steps '1.2. Specify EDA Tool Settings'onwords from attached link & use testbench name 'pll_vlg_tst' instead of testbench_1 & browse the .vt file. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf 5. Eventually, when you perform 'Click Tools ➤ Run Simulation Tool ➤ RTL Simulation ' it will take time to open modelsim. please let me know if you have any different concern. Regards, Vikas