.mif file generation of perticular freuency

Hi,

The frequency depends on your Fs i.e. f = Fs/Number of points per cycle.

To generate one sinusoid cycle of n points in Matlab and quantising onto 16 bits signed:

data = sin(2*pi*[0:n-1]/n);

data = round(data* (2^15-1)/max(data));

you can then display data as a column, copy and paste to a mif file(This is quicker than writing mif text)

Kaz

hi..thanks Kaz...but actually i have to implement the .mif for perticular frequency like 480 Hz in verilog itself...for that i have to generate a tone by storing this .mif file into Rom.

actually i don't know about Matlab...so

Hi,

If your problem is DSP-builder tool related then I hope somebody else may help.

However, if you want to generate 480Hz by hand then if your effective clock frequency for the module is say 0.48MHz then you need to generate mif file for rom having 1000 points. This mif file will be good for verilog or vhdl module. Thus to avoid large rom use a low frequency clock.

If you enter Matlab as n= 1000 with my previous statements then you get the data ready. All you have to do is copy and paste to new mif in Qartus(file-> new-> oters ->mif), you will get spread-sheet style of mif. Then set data to 2's complement and paste.

Kaz

In this post

http://www.alteraforum.com/forum/showthread.php?t=3448

There is a matlab function that can help you to generate the .mif file.

This is where VHDL is significantly more flexible than Verilog. Since VHDL supports all the floating point operations naturally and doesn't complain when a "real" type is being manipulated during synthesis, you can actually code this up extremely generically.

library ieee ;
  use ieee.std_logic_1164.all ;
  use ieee.numeric_std.all ;
  use ieee.math_real.all ;
entity complex_tone_ram is
  generic (
    FREQ_SAMPLE :   real        :=  50.0e6 ;
    FREQ_TONE   :   real        :=  4.096e6 ;
    Q           :   positive    :=  12 ;
    WIDTH       :   positive    :=  15
  ) ;
  port (
    clock       :   in  std_logic ;
    sreset      :   in  std_logic ;
    enable      :   in  std_logic ;
    i_out       :   out signed(WIDTH-1 downto 0) ;
    q_out       :   out signed(WIDTH-1 downto 0)
  ) ;
end entity ; -- complex_tone_ram
architecture arch of complex_tone_ram is
    -- Naive search for LCM between sample rate and tone to be generated
    function calculate_num_points( sample_rate, tone : real ) return integer is
        variable retval : integer ;
    begin
        retval := 1 ;
        while( (tone*real(retval)/sample_rate) mod 1.0 /= 0.0 ) loop
            retval := retval + 1 ;
        end loop ;
        return retval ;
    end function ;
    
    -- A constant to hold the number of points
    constant NUM_POINTS : integer := calculate_num_points( FREQ_SAMPLE, FREQ_TONE ) ;
    
    -- The RAM type that will be inferred
    type ram_t is array(NUM_POINTS-1 downto 0) of signed(WIDTH-1 downto 0) ;
    
    -- A function to populate the RAM
    function populate_ram( phase_increment, scale : real ) return ram_t is
        variable retval : ram_t := (others =>(others =>'0')) ;
    begin
        for i in retval'range loop
            retval(i) := to_signed(integer(round(scale*cos(phase_increment*real(i)))), retval(i)'length) ;
        end loop ;
        return retval ;
    end function ;
    
    -- The RAM signal itself
    signal ram : ram_t := populate_ram( FREQ_TONE/FREQ_SAMPLE * MATH_2_PI, real(2**Q) ) ;
    -- Find the location which is 90 degrees out of phase with 1.0
    function find_q_start_address( ram : ram_t ) return integer is
        variable retval : integer ;
    begin
        retval := 0 ;
        for i in ram'range loop
            if( ram(i) = 0 and ram(i+1) > 0 ) then
                retval := i ;
            end if ;
        end loop ;
        return retval ;
    end function ;
    constant I_START_ADDRESS : integer := 0 ;
    constant Q_START_ADDRESS : integer := find_q_start_address( populate_ram( FREQ_TONE/FREQ_SAMPLE * MATH_2_PI, real(2**Q) ) ) ;
    -- I and Q address signals
    signal i_address    :   integer range ram_t'range := I_START_ADDRESS ;
    signal q_address    :   integer range ram_t'range := Q_START_ADDRESS ;
begin
    
    generate_addresses : process( clock )
    begin
        if( rising_edge( clock ) ) then
            if( sreset = '1' ) then
                i_address <= I_START_ADDRESS ;
                q_address <= Q_START_ADDRESS ;
            else
                if( enable = '1' ) then
                    if( i_address = ram'high ) then
                        i_address <= 0 ;
                    else
                        i_address <= i_address + 1 ;
                    end if ;
                    
                    if( q_address = ram'high ) then
                        q_address <= 0 ;
                    else
                        q_address <= q_address + 1 ;
                    end if ;
                end if ;
            end if ;
        end if ;
    end process ;
    
    create_tone_output : process( clock )
    begin
        if( rising_edge( clock ) ) then
            i_out <= ram(i_address) ;
            q_out <= ram(q_address) ;
        end if ;
    end process ;
end architecture ; -- arch

All will be done at compile time for any particular complex frequency. Obviously this can be adapted to be a real-only tone generator as well.

NOTE: Quartus II has an issue with performing a loop more than 10,000 times, but I believe that check can be disabled if you require.

EDIT: Also note the Q starting address with be in-phase with the I starting address if the number of sample points is not divisible by 4.

hi ,

thanx for this vhdl code..

can u tell me how much frequency of signal it will generate.....

actually i have to generate a frequency of 425Hz ...so for that what changes i have to make in this code.....

No.

The code is well written and easy enough to simulate.

If you honestly don't know where to make the changes, I suggest you pick up a good VHDL book and start reading.

Good luck!

hi . i made the the changes :

FREQ_TONE : real := 425e0 ;

but after that when i compiled it gives an error..

can u help me regarding this

you also need to enter the freq_sample as your clock's actual frequency.

However although this code is well written it fails at some values...

Moreover I am not sure if it gives phase continuity correctly. It is also rigid and may be good for one particular frequency but could result in very large memory especially for small values of tone relative to clock.

You better use Altera NCO compiler. This is more versatile and can generate any frequency less than clk/2 including very very fine steps by simply changing the tuning word value.

kaz

hi Kaz..

thanx ..but can u tell me the settings i have to do in NCO compiler for generating a frequency of 425 Hz...

it will generate the mif file of that frequency or anything else??

plz tell me soon