请教使用10AX115S3F45E3SG器件实现4个40GE IP加48个1G/10GE IP管脚分配编译不过问题

HI,

The main factor that will affect fitter error would be XCVR channel pin placement and also PLL resource usage.

• But I can only comment further after I reviewed your design first.
• Another tip to debug fitter error will be to let Quartus auto fit as much as possible to test out whether it's possible to fit in your user design requirement first on this specific FPGA package
• Also can you share with me your design QAR file to help me understand the fitter error better ?

The main restriction will be user can't use same PLL to support different data rate. (for instance : 1G vs 10G data rate switching)

1. For 1G/10G PHY IP - it required one pair of Tx/Rx channel + 1G PLL (CMU/fPLL) + 10G PLL (ATX/CMU)
2. For 40G IP - it required four pair of Tx/Rx channel + 10G PLL (ATX/CMU)

Thanks.

Regards,

d