Forum Discussion
XCVR Reset Controller
Hi,
So, is this quote from the document above a hard requirement? -> Yes
ADC needs clock before FPGA gets programmed. Else you need to program it twice.
Regards,
Harsh M
- David321 year ago
Occasional Contributor
Thanks for this info Harsh.
It will take me some time to be able to test this.
Please either leave this thread open for about a month or maybe I will just re-open it once I have progressed a bit.
David
- David321 year ago
Occasional Contributor
Hello Harsh,
I have modified the environment so now the reference clock to the JESD receiver is stable when the FPGA comes out of configuration.
On Signal Tap I am still seeing that the rx_is_lockedtodata signals (I have 4 lanes in my device) randomly toggle.
In the first attached screenshot you can see that all signals become locked and then the digital resets become inactivated.
In the second screenshot I show the opposite, when one of rx_is_lockedtodata becomes false causing the reset to become active.
How can I proceed to tackle this problem?
Thanks
David
- David321 year ago
Occasional Contributor
Hi Harsh,
I thought of using the Transceiver Toolkit to help track down the problem.
I made sure that all the necessary options in the JESD IP were enabled (dynamic reconfiguration, etc), and connected the signals in QSYS to a JTAG Master.
The JTAG Master is recognized in System Console but the Toolkit does not recognize any debug endpoint.
Could you please also help with this.
Thanks
David