XAUI Phy in Stratix IV GX

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the lanes are scrambled. If I send at tx_datain X"FFEEDDCCBBAA9988" the I receive at rx_dataout X"EEFFCCDDAABB8899".

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Your original description is ambiguous. The lanes (wires on the board) are not scrambled, the data from a lane is scrambled.

Look at the pattern - what do you see?

FFEE DDCC BBAA 9988

EEFF CCDD AABB 8899

Each 16-bit value has the bytes swapped. Now look in the Stratix IV user manual. You will find there is a FIFO that can cause this byte-swapping. You need to use the synchronization controls to align to a pattern; look at rx_byteorderalign and rx_enapatternalign, there is also a byte-reversal feature you can use (if you do not control the source of the data).

However, I would have thought XAUI would have taken care of this for you, by initializing the link with sync codes.

Cheers,

Dave