Honored Contributor
Honored ContributorHi Dave,
the lanes are scrambled. If I send at tx_datain X"FFEEDDCCBBAA9988" the I receive at rx_dataout X"EEFFCCDDAABB8899". (see attached signal tap screenshots tx_datain.jpg and rx_dataout.jpg) In some cases the alignment is correct (rx_dataout2.jpg). Before sending the data I use two start packets. The transmission of these packets is always incorrect (see the screenshots). Which megafunction you are using? ALTGX and ALTGX_RECONFIG? What are your parameter settings? (if you want have a look at my settings, see params at the end of reply) Which clocks you re using? I use for XAUI Refclk the LVDS clock source at pin AA2 (156.25 MHz) For the dynamic reconfiguration circuit I'm using the freerunning clock clkin_50 at pin AC34. The data generator is clocked with the coreclockout from ALTGX block. How is your implementation of the reset controller for ALTGX_RECONFIG? My reset sequence is like in the Stratix IV Device Handbook Volume 2: Transceivers, page 4-8, figure 4-4. (see attached altgx_reset1.jpg and altgx_reset2.jpg) There just is one difference. In my case the busy signal is always '0'. How do you verfy the transmission? With external or internal loopback? p.s. I try using the XAUI_PHY (external reconfig is not required) like in the example for Stratix V. I didn't succeed. (tx_ready and rx_ready signals are always '0') Jens --------------------------------------- ALTGX settings --------------------------------------- General protocol: xaui nr of channels: 4 channel width: 16 effective data rate: 3125 clock freq.: 156.25 base data rate: 3125.0 PLL/ports train transceiver clock : enabled optional ports: enabled ports/calibration analog power: auto Rx analog static equalizer ctrl: disabled DC gain: 0 common mode voltage: 0.82 termination resistance: 100 ohm Tx analog transmitter buffer power: auto transmitter common mode voltage: 0.65 transmitter termination: 100 ohm next parameter all to 0 Reconfig sttings just offset cancellation is enabled
