Occasional Contributor
Regular ContributorHi,
May I know what is the data length that you are using during write? Do you have issue in writing 32bit of data every time? Or it is happening during burst write?
Can you share the SignalTap or design to further understand your issue?
Occasional Contributorhii yes
i write a 32 bit of data on avmm_data_writedata on the avalon bus , and i set the burstcount to 1
i hold the avmm_write<='1' as long as waitrequest=1 , and when i receive waitrequest=0 i disable the avmm_write , update the next address and move to the next data to write
As noted earlier, write operations generally succeed when I verify the success flags in the CSR status register. However, I occasionally encounter a write failure when writing a 32-bit word, even though previous writes completed successfully.
Regular ContributorHi,
May I know how frequent are you facing the write failure? May I know if your design has any timing issue?
Occasional Contributorhii
I receive the RPD data through a serial UART interface, and I can control the time delay between each transmitted word (4 bytes). What I noticed is that when the delay is about 2.5 ms between each word, I can write the RPD successfully without errors.
However, when I try to decrease the delay between the words down to 1.5 ms, I start to get these errors.
My logic performs the write operation and verifies the write success within the delay period between the words received through the UART.
I should also state that I used a 50 MHz clock for my design. I tried lowering the clock frequency to see if it would help, so currently my system is running at 50 MHz.
I also observed the waitrequest signal by routing it to a header pin on my board and probing it with my own logic analyzer. I noticed that the pulse width of the waitrequest signal ranges from a few hundred microseconds up to more than 1000 microseconds and even more. However, the datasheet states that the maximum pulse width should be around 350 microseconds, which is not the timing I am seeing on the logic analyzer.
Is the pulse width of the waitrequest signal that I observed on the logic analyzer normal?
I checked my design and found that there is indeed a timing issue that I still need to fix. However, I encounter these errors only when I decrease the delay between the words sent through the serial UART in order to reduce the time needed to update the new image in the FPGA CFM.
