Please see post# 6 for a better formulation of the problem. ------ Hi! I have a question about the memory blocks that are available on the Altera FPGA chips. Is it possible to write the same data to multiple locations of a memory block? Example: I want to write the value 7 to locations 0, 1, 2, and 3 of the memory block. I want to do it in one clock cycle. It is possible to do in ASIC with a custom memory controller. Is it possible in FPGA? Alex

Some memories with multiple ports(dual,quad) allow for that but not single port memory. You can also put your data on 4 lanes on a wide memory to rd/wr in one clock cycle.

To add to the discussion... [1] Do these memory blocks provide write_enable signals for each word? This would allow me to write a controller that does this easily. [2] Also, could the Megafunction feature help with this? Alex

#1 Yes they do, and often expose byte enables too depending on how you setup the memory. # 2 I recommend using the megafunction since it'll guide you to the options that are supported. After a while you will become familiar enough that you may not need to use it anymore and can instantiate the memory directly (or just infer it). Also I recommend going to the handbook of whatever device you plan on targeting and looking at the memory block chapter. Near the beginning of that chapter it will show you all the block types you have at your disposal and the modes they can be used in. At most you will only be able to write to two memory locations concurrently but like Kaz mentioned you can work around this limitation. Another workaround is if you know the access pattern you might be able to segment your memory into separate blocks and access multiple blocks in parallel (maybe even addresses go to block 1 and odd addresses go to block 2).

Thanks for your replies! I will try these approaches soon, and come back with results. And, BadOmen, GO HABS GO! (I am from the area ;)

OK. I've played a bit with the Megafunction tool and it seems that the memory interfaces it provides are not exactly what I need. Here is a rephrased problem statements: Imagine you have a 128x8bit memory initialized to zero. I want to be able to write "tail"-sections of this memory with the same value in one clock-cycle. Note that I always write from an index i till the end. (I call it a "tail"-section) Example: Write from location 64 to 127 the value 7. Result: half memory is zero half is 7. Write from location 96 to 127 the value 8. Result: half memory is zero, one quarter 7, other quarter 8. This kind of writes are trivial to implement if each memory word (location) provides a write_enable control signal, so that I could enable and disable it accordingly. The question is how do I do in on a Stratix IV chip (EP4SGX230)? I see that I have the following embedded memories: MLAB (640bit) M9K (9kbit) M144K (144kbit) Do any of these extend the write_enable control signals for each word? If not what is the most compact way to implement the memory I have described?

write to segment (multiple locations) of memory

12 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Writing same value or different values does not make it any easier for ram access. There are as many ports as vendors have decided.
I believe you better use register array indexed as ram
--- Quote End ---

[1]
You are right if you consider the M9K, M144K to be RAMs. Somehow I thought these are generic memory blocks that can implement various types of memory: random access, FIFO, etc.

[2]
What is the most detailed information about the M9K (and the like) memory blocks available? I have the stratix iv hanbook (http://www.altera.com/literature/hb/stratix-iv/stratix4_handbook.pdf) (chapter 3), but it still does not answer all my questions.

[QUESTION I STILL HAVE]
1. How do I write VHDL code to tell Quartus tools to put a certain memory into a M9K, or M144K, or other block?
Altera_Forum
Honored Contributor
14 years ago
Hi,

memory blocks are -as you certainly know - are ASIC like memory structures within fpgas accessible to logic through their ports and configurable through megawizard or code... into rams or roms or fifos or shift function.
I don't know what you mean exactly by memory block as opposed to these blocks. a ram has access through its ports, so is the rom and so is fifo or shift function.

You will need to click on megawizard (tool menu) and choose memory compiler then choose your configuration.

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write to segment (multiple locations) of memory

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