Altera_ForumHonored Contributor10 years agoWrite contention on dual-ported M9K blocks I've an M9K memory block configured as 'true dual port' with a single clock and OLD_DATA. I know that if both ports write to the same location then the written data is undefined. Does any...Show More
Altera_ForumHonored Contributor10 years agoFurther investigation has shown that it was all my fault :-(
Recent DiscussionsWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File InformationCyclone 10 LP's Extended Industrial parts