Hello everyone, I want to make something that records values that are in my FPGA. I thought of using the Cyclone V SoC DMA, I do have the Altera SoC kit. With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA? I want to set a trigger in the HPS DMA, so that when I send a signal to high level at FPGA Fabric, the DMA starts to copy a FPGA FABRIC RAM content to the DDR connected in the HPS and visible by the Linux running in the ARM. *Is this the easiest/fastest way of achieving what I want?

HPS and FPGA connected through AMBA bus. If HPS-DMA registers visible from FPGA, 2nd may signal to 1st. *And why you do not write data to HPS memory from FPGA direct in process accumulation as possible ?

There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over).

--- Quote Start --- There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over). --- Quote End --- BadOmen do you have a link for a ref design or something that uses it that way? As far as I can see, I will need to limit a SDRAM area for the HPS, right? And reserve some for my FPGA fabric. I am finding very hard to find ref. designs for the HPS interacting with the FPGA. Thanks for your answer, looks like the best way to do it. Maybe with a DMA (FPGA fabric) pushing to the SDRAM C

Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later. I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.

--- Quote Start --- Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later. I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it. --- Quote End --- Yup I saw this ref design, however it uses the F2H and H2F bridges and not the F2SDRAM, Can I just instiantiate a DMA IP in QSys and connect to the F2SDRAM bridge? QSys magically takes care of everything for me? Could you share with me this "beta design" you have? My e-mail is wcprado { AT } hotmail { dot } com

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

22 Replies

Altera_Forum
Honored Contributor
12 years ago
Yes F2S, sorry for the typo.

Thanks for your help BadOmen, going to handle the FPGA Design to the firmware team and let's see if it works :)

Cheers
Altera_Forum
Honored Contributor
12 years ago
Where can find the reference design of F2S usage ?
Altera_Forum
Honored Contributor
12 years ago
So, I've tried this architecture and it worked!!!

However I am getting only 150MB/s throughtput, I expected around 300MB/s

I just took a look in the DMA Core and Enabled the Burst transfer. Then I configured it to 1024 max words. And I've also increased the FIFO depth to 256. I am going to try and see the results.

In the Address span extender, my data width is set to 64 bits. The burstcount Width is 1 bit and maximum pending reads is also set to 1.

Any ideas on a configuration that could help the throughput?

--- Quote Start ---
As long as when you say "F2H" you really mean F2S (i.e. the HPS SDRAM dedicated ports) then yes this is the correct way to set up the hardware. You can probably reduce the DMA length register width since you are only exposing 512kB of memory in the HPS at a time.

Make sure the DMA control port is connected to the lightweight HPS-to-FPGA bridge so that MPU can tell the DMA what to do.
--- Quote End ---
Altera_Forum
Honored Contributor
12 years ago
Well with the Enabled Burst Transfer no more IRQs comes from the DMA.
Altera_Forum
Honored Contributor
12 years ago
I've tried some configurations with the DMA and the mem addr spammer but without success, can't get past 150MB/sec in the HW side... :(
Altera_Forum
Honored Contributor
12 years ago
So, I've increased the data width of the onchip ram to 64 bits and enabled only words/double-words transfers in the DMA.

With this I was able to get 224MB/Sec, a little bit better.

Final update:

The device driver wasn't enabling the double word transfer, with it enabled now I am hitting 324MBytes/Sec.
Altera_Forum
Honored Contributor
12 years ago
hi aprado,

I have do the QSYS interconnect as you mentions, but after trig DMA, it stay with BUSY bit, and can't go through...

Can you share your design for me ? ( FPGA project or QSYS file)
[email protected]

Thanks in advance.

Lucian
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
So, I've increased the data width of the onchip ram to 64 bits and enabled only words/double-words transfers in the DMA.

With this I was able to get 224MB/Sec, a little bit better.

Final update:

The device driver wasn't enabling the double word transfer, with it enabled now I am hitting 324MBytes/Sec.
--- Quote End ---

Hi Aprado,

Would it be possible that you posted your design or possibly email me? I'm trying to do a similar task but I'm having issues with the dma and how it gets controlled by hps.

[email protected]
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
Hi Aprado,

Would it be possible that you posted your design or possibly email me? I'm trying to do a similar task but I'm having issues with the dma and how it gets controlled by hps.

[email protected]
--- Quote End ---

I am also very interested in example driver code for controlling the DMA from the HPS. Would you please share?
[email protected]
Altera_Forum
Honored Contributor
10 years ago
Hi aprado,

Is it possible to share your design to [email protected] please. I am also have the same thing to do, but struggling to get it done.

Best Regards.

Forum Discussion

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

22 Replies

Recent Discussions

Agilex5 NSATUS signal behavior at power up.

TSE MAC+PCS (SGMII, Cyclone 10 GX): mdio_out/mdio_oen never toggle, no matter what I write

Cyclon 5 tampering protection bit

10CL040YF484 Programming fails

Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound