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Altera_Forum
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11 years ago

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

Hello everyone, I want to make something that records values that are in my FPGA. I thought of using the Cyclone V SoC DMA, I do have the Altera SoC kit. With the Cyclone V SoC, how can I ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

So, I've tried this architecture and it worked!!!

However I am getting only 150MB/s throughtput, I expected around 300MB/s

I just took a look in the DMA Core and Enabled the Burst transfer. Then I configured it to 1024 max words. And I've also increased the FIFO depth to 256. I am going to try and see the results.

In the Address span extender, my data width is set to 64 bits. The burstcount Width is 1 bit and maximum pending reads is also set to 1.

Any ideas on a configuration that could help the throughput?

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As long as when you say "F2H" you really mean F2S (i.e. the HPS SDRAM dedicated ports) then yes this is the correct way to set up the hardware. You can probably reduce the DMA length register width since you are only exposing 512kB of memory in the HPS at a time.

Make sure the DMA control port is connected to the lightweight HPS-to-FPGA bridge so that MPU can tell the DMA what to do.

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