Hello everyone, I want to make something that records values that are in my FPGA. I thought of using the Cyclone V SoC DMA, I do have the Altera SoC kit. With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA? I want to set a trigger in the HPS DMA, so that when I send a signal to high level at FPGA Fabric, the DMA starts to copy a FPGA FABRIC RAM content to the DDR connected in the HPS and visible by the Linux running in the ARM. *Is this the easiest/fastest way of achieving what I want?

HPS and FPGA connected through AMBA bus. If HPS-DMA registers visible from FPGA, 2nd may signal to 1st. *And why you do not write data to HPS memory from FPGA direct in process accumulation as possible ?

There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over).

--- Quote Start --- There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over). --- Quote End --- BadOmen do you have a link for a ref design or something that uses it that way? As far as I can see, I will need to limit a SDRAM area for the HPS, right? And reserve some for my FPGA fabric. I am finding very hard to find ref. designs for the HPS interacting with the FPGA. Thanks for your answer, looks like the best way to do it. Maybe with a DMA (FPGA fabric) pushing to the SDRAM C

Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later. I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.

--- Quote Start --- Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later. I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it. --- Quote End --- Yup I saw this ref design, however it uses the F2H and H2F bridges and not the F2SDRAM, Can I just instiantiate a DMA IP in QSys and connect to the F2SDRAM bridge? QSys magically takes care of everything for me? Could you share with me this "beta design" you have? My e-mail is wcprado { AT } hotmail { dot } com

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

22 Replies

Altera_Forum
Honored Contributor
12 years ago
HPS and FPGA connected through AMBA bus.
If HPS-DMA registers visible from FPGA, 2nd may signal to 1st.
*And why you do not write data to HPS memory from FPGA direct in process accumulation as possible ?
Altera_Forum
Honored Contributor
12 years ago
There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over).
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
There are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over).
--- Quote End ---

BadOmen do you have a link for a ref design or something that uses it that way? As far as I can see, I will need to limit a SDRAM area for the HPS, right? And reserve some for my FPGA fabric. I am finding very hard to find ref. designs for the HPS interacting with the FPGA.

Thanks for your answer, looks like the best way to do it. Maybe with a DMA (FPGA fabric) pushing to the SDRAM C
Altera_Forum
Honored Contributor
12 years ago
Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later.

I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later.

I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.
--- Quote End ---

Yup I saw this ref design, however it uses the F2H and H2F bridges and not the F2SDRAM, Can I just instiantiate a DMA IP in QSys and connect to the F2SDRAM bridge? QSys magically takes care of everything for me?

Could you share with me this "beta design" you have? My e-mail is wcprado { AT } hotmail { dot } com
Altera_Forum
Honored Contributor
12 years ago
You hit the nail on the head, Qsys will take care of any adaptation between the soft DMA logic and the interface into the HPS, that's why I use Qsys for integration because then I just worry about the IP being compliant to the interface spec and the tools will take care of gluing the IP together for me.

Unfortunately the design isn't very far along so it would be quicker to integrate it yourself. You would connect the lightweight H2F bridge to the slave port of the DMA so that the Cortex-A9 can control the DMA then connect the DMA masters to the HPS SDRAM ports. I said "ports" because you could have one port dedicated to reads and the other dedicated to writes and perform both reads and writes simulataneously and the HPS SDRAM controller will interleave them out to memory for you. If you use an existing DMA then I would select Avalon-MM ports for the SDRAM interface into the FPGA since the DMAs in Qsys are already Avalon-MM based (you can mix Avalon and AXI but that's just a waste of logic resources in this case).
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
You hit the nail on the head, Qsys will take care of any adaptation between the soft DMA logic and the interface into the HPS, that's why I use Qsys for integration because then I just worry about the IP being compliant to the interface spec and the tools will take care of gluing the IP together for me.

Unfortunately the design isn't very far along so it would be quicker to integrate it yourself. You would connect the lightweight H2F bridge to the slave port of the DMA so that the Cortex-A9 can control the DMA then connect the DMA masters to the HPS SDRAM ports. I said "ports" because you could have one port dedicated to reads and the other dedicated to writes and perform both reads and writes simulataneously and the HPS SDRAM controller will interleave them out to memory for you. If you use an existing DMA then I would select Avalon-MM ports for the SDRAM interface into the FPGA since the DMAs in Qsys are already Avalon-MM based (you can mix Avalon and AXI but that's just a waste of logic resources in this case).
--- Quote End ---

Thanks BadOmen, gonna try this.

I saw you talking about a SDRAM Memory Address Spammer or something like that, do I need it? What is it used for?
Altera_Forum
Honored Contributor
12 years ago
The F2S interfaces expose a 4GB address space so if your DMA is limitted in it's addressing capabilities you might need to put that address span bridge between it and the HPS. The DMA and SGDMA in Qsys only support up to 4GB but the mSGDMA up on alterawiki.com supports up to 64-bit addressing if you enable the enhanced descriptors. So if you used the mSGDMA you wouldn't need the address span bridge.

Regardless of the DMA addressing capabilities you might want to expose only a subset of the full 4GB SDRAM range so that the addressing logic in the DMA is not as wide. That typically drops the Fmax of the design when you try to master lots of memory so you might want to limit the address span using the address span bridge. For example lets say you only want to make addresses 0x1000_0000 to 0x100F_FFFF (1MB window) available you could setup the address span bridge to expose a 1MB range and have it hardcoded to start at 0x1000_0000.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
The F2S interfaces expose a 4GB address space so if your DMA is limitted in it's addressing capabilities you might need to put that address span bridge between it and the HPS. The DMA and SGDMA in Qsys only support up to 4GB but the mSGDMA up on alterawiki.com supports up to 64-bit addressing if you enable the enhanced descriptors. So if you used the mSGDMA you wouldn't need the address span bridge.

Regardless of the DMA addressing capabilities you might want to expose only a subset of the full 4GB SDRAM range so that the addressing logic in the DMA is not as wide. That typically drops the Fmax of the design when you try to master lots of memory so you might want to limit the address span using the address span bridge. For example lets say you only want to make addresses 0x1000_0000 to 0x100F_FFFF (1MB window) available you could setup the address span bridge to expose a 1MB range and have it hardcoded to start at 0x1000_0000.
--- Quote End ---

I see! It makes sense.

I guess the same goes for the FPGA->SDRAM bridge with Altera Qsys DMA.

Just to make sure.

1. I've set the F2S SDRAM Bridge data to 64 bits WIDTH and write only, avalon-mm
2. I've added a SPAN EXTENDER, then i set the DATA PATH WIDTH to 64 bits and the ADDRESS WIDTH of the master to 32 bits (4 giga) and a default subwindow of 512kb
3. I've added an ALTERA DMA Controller and the WIDTH of the DMA LENGTH REGISTER is set to 32 bits
4. I've connected the DMA write master to the windowed slave on the SPAN EXTENDER
5. I've connected the expanded master to F2H_DATA

That's it? Now the Device Driver on HPS must set the right registers on the DMA Control port slave.
Altera_Forum
Honored Contributor
12 years ago
As long as when you say "F2H" you really mean F2S (i.e. the HPS SDRAM dedicated ports) then yes this is the correct way to set up the hardware. You can probably reduce the DMA length register width since you are only exposing 512kB of memory in the HPS at a time.

Make sure the DMA control port is connected to the lightweight HPS-to-FPGA bridge so that MPU can tell the DMA what to do.

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With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

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