Will sending data from serial port to FPGA change the existing layout

I designed a module that uses direct counting to measure signal delay through a circuit. One of the parameters is stored in a register and assigned using an external serial port. I used signal tap to capture the measurement results of circuit delay and found that without re burning, the measurement results of circuit delay were stable (with fluctuations not exceeding my measurement accuracy). But later it was found that modifying this parameter through the serial port would affect the measured circuit delay results, and the magnitude of the change would be huge, reaching more than 10ns (I think even considering the temperature effect is too large). May I ask what may be the reason for this and how can we explain this phenomenon from the underlying structure? This module is a part of the company's project, and I cannot directly send out the code. Please forgive me.