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Am I right in assuming only few slaves can connect to F2SDRAM at a time and hence the width of it is limited to 4?
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To clarify, you are asking about the number of masters (not slaves) that will connect to the F2SDRAM port. The number of supported masters depends on their AXI ID width.
If the masters have a width of 4, then only one can be connected.
If the masters have a width of 3, then 2 of them can be connected (the "extra" ID bit is used to distinguish between the two masters).
If the masters have a width of 2, then 4 of them can be connected (the extra 2 ID bits are used to distinguish between the 4 masters).
If the masters have a width of 1, then 8 of them can be connected (the extra 3 bits are used to distinguish between the 8 masters).
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