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Altera_Forum
Honored Contributor
Honored ContributorWidth of Slave id(4) must be min 5. Increase slave ID width or reduce connected maste
Hello, I have used the Arria 10 Soc design from rocketboard to which I am making few modifications. I am getting the following error in qsys when I exceed a particular number of connections.(to H...
Altera_ForumHonored Contributor
Honored ContributorThank you sstrell and sslock for the information.The AXI bridge idea worked. I was able to take it through synthesis flow also without any error.
Am I right in assuming only few slaves can connect to F2SDRAM at a time and hence the width of it is limited to 4?
