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Altera_Forum's avatar
Altera_Forum
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8 years ago

Width of Slave id(4) must be min 5. Increase slave ID width or reduce connected maste

Hello, I have used the Arria 10 Soc design from rocketboard to which I am making few modifications. I am getting the following error in qsys when I exceed a particular number of connections.(to H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The ID widths of the masters connected to the F2SDRAM bridge exceeds the ID width (4) of the F2SDRAM bridge slave port. If you can, reduce the size of the masters connected to the F2SDRAM port. If you cannot do this, then place an AXI Bridge in front of the F2SDRAM bridge. You can set the ID width of the master interface (connects to the F2SDRAM bridge) to 4 and set the ID width of the slave interface (connects to your other masters) to a higher value.