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Altera_Forum
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8 years ago

Width of Slave id(4) must be min 5. Increase slave ID width or reduce connected maste

Hello, I have used the Arria 10 Soc design from rocketboard to which I am making few modifications. I am getting the following error in qsys when I exceed a particular number of connections.(to H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank you sstrell for the reply.I have already done that.

I am using the F2SDRAM bridge in my design.The F2SDRAM bridge doesn't work if the conduit for emif is not enabled in HPS.

Any other idea?

As i go on increasing the number of slaves connected to HPS, the error is being modified to the below:

Error: arria10_hps_f2sdram0_data: Width of Slave ID signals (4) must be atleast 7. Increase slave ID width or reduce widths for any connected AXI master