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joe306's avatar
joe306
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Why the newer FPGA's do not support 3.3V LVCMOS?

Hello, I noticed that the newer FPGA's (Cyclone 10, Arria 10, Stratix 10) do not support 3.3V LVCMOS only 3V IO. Doesn't this limit the number of devices that you can interface with and why did Intel choose 3V IO?

Thanks,

Joe

2 Replies

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi ,

    Most of the current devices support 3V LVCMOS that is the reason for the support 3V LVMOS standard.

    Regarsd,

    RS

  • joe306's avatar
    joe306
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    I think we are seeing the beginning of the trend to lower power from 3.3V devices to 2.5V just as we saw the 5V devices move down to the 3.3V devices. Xilinx FPGAs, even the newer ones, still support 3.3V devices. Xilinx FPGAs have High-range pins (1.2V to 3.3V) IO and High-performance pins (1.2V to 1.8V) IO.