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Altera_Forum
Honored Contributor
14 years agoWhy Quartus cannot recognise my state machine
Hi all, We have implemented a state machine in a Stratix V project however we cannot find it in either state machine viewer or compilation report. Could anyone give some hints that does Quartus...
Altera_Forum
Honored Contributor
14 years agoThanks. However the state machine still does not behave even after registering all the external signals...We are pretty sure that the state switch logic described in the code is correct. We have signaltapped the internal signals and it seems that the state will jump to another unrelated one even all the triggers are correct, or will not quit current state when it shoud do.
BTW, if we use state variable declared in this way: reg [6:0] state, next_state; parameter S0=1, S1=2, S2=3... Should we expect to see the 7-bit state variable in signaltap? Currently we can only find state.S0 state.S1 ... in signaltap, which are all single-bit signals. Thanks