Forum Discussion
Altera_Forum
Honored Contributor
18 years agoI have solved it.
In Quartus II, i use simulation to simulate the whole process. In the Simulation Report, it uses about 50us to finish the RDSR, WREN, WRSR and SECTOR-ERASE steps. Then I execute RDSR again to find out whether the erase cycle is still in progress. It uses about 500us to finish SECTOR-ERASE step and set Bit0 to 0. Since the time step which i set in simulation is small(about 150ns), i didn't find the termination of SECTOR-ERASE and thought that the Bit0 was always high. Now, it can work correctly now.