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Hello All ,
Actually , reset is not requried for the PLL reconfiguration
If a reset is asserted , all the settings of reconfiguration will be lost
For example , in the mif file , the initial phase of the PLL is 0
After the reconfiguration , the phase is increased by one
If a reset is asserted , the Phase of PLL will return to 0 , instead of the value that user has set
I have verified it on the Silicon Device
Regards ,
Samson
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So how did you get the PLL to reacquire a lock? I've got a design that forces me to change the N value on occasion, and I can't get it to reacquire the clock. I've tried asserting reset and areset, with neither having any effect. I've run out the timing simulation to 100us, with it losing lock around 3us. It reacquires the lock if I run a functional simulation, but not if I run a timing simulation.
BTW, I'm using Quartus 6.0SP1 and a Stratix II device.
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