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To answer the first question of what does that line do.....
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Now that was a rhetorical question.
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(Well) written verilog should be readable by VHDL developers
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The catch is in 'well written' that well isn't good enough, it must be impeccably written (even for the sake of the Verilog user). Take a look at the DDR2 EXample Driver .v source and you'll see what I mean. I already bought my first Verilog book several months ago, but my workload is high enough to leave no time to experiment. Verilog is not that hard to read and modify, but there are some subtleties like blocking and non-blocking (and a few more?0 I'll have to study.
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Maintaining dual language generation or writing IP cores in two languages is a huge maintenance burden so that's the reason for the shift to verilog and system verilog. In terms of testing, system verilog offers much more so the only sane choice is to shift to system verilog. VHDL will probably catch up on the test side but by the time they do it might be too late....
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As I said before, it is perfectly OK to have IP written in Verilog (or any other language). I do not test 'large' systems so I am perfectly OK with VHDL and the internal simulator to test my small building blocks (Avalon ST-like) which can be connected together and operate very predictably. Shifting over to Verilog means to re-write of my VHDL support packages.
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And before anyone tries to start a VHDL vs verilog war
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I certainly don't want to start a war ...
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