Why is Altera force-feeding us with Verilog?

Maintaining dual language generation or writing IP cores in two languages is a huge maintenance burden so that's the reason for the shift to verilog and system verilog. In terms of testing, system verilog offers much more so the only sane choice is to shift to system verilog. VHDL will probably catch up on the test side but by the time they do it might be too late....

To answer the first question of what does that line do..... if I remember correctly that will evaluate to a 1. Again like others have said this is the price paid for having dual language support that is machine generated, it's not pretty and increases the testing burden. (Well) written verilog should be readable by VHDL developers for the most part and visa versa so that's the direction we are moving towards instead of generated code that is difficult to understand.

And before anyone tries to start a VHDL vs verilog war.... don't bother since I'll just lock the thread since it's a waste of forum storage.....