Forum Discussion
Occasional ContributorWhy does Agilex-F PCIe RP IP example design assign the P0 to PCIe lane#0-3 instead of lane#4-7 ?
Ok after understanding further by checking the ED Qsys (platform designer).
I can see the JTAG master component is connecting to P0 of the P-tile IP. By right it should connect to channel 4-7 based on table 57. However, we not sure why ED connects it to 0-3, I will check this with the internal team but will need some time.
However, for urgent sake, you can try the approach by using lane 4-7 for the example design. If not working, then we will give a try on other port (by changing the connection in the Qsys) or another lane on assignment editor.
Frequent ContributorFor PCIe link configuration, it will configure based on the effective lane. For example, an upstream device has X16 lane. However, the down stream device only has x4 lane, regardless you connect the x4 downstream device to which lane order of the upstream device (mean regardless to you connect it to lane 0-3 or 4-7). The upstream device will proceed with a group of lanes that can still be used to create a link. Mean it will link up with x4 configuration. In this case, the link-up is 1-1, same with what we want to achieve in the example design. This is not a bifurcation mode.
For bifurcation mode, it is referring to splitting 1 PCIe Port into 2 or more with smaller lane width. Example an upstream x16 port into 2downstream x8 port. In this case, the link up is 1 to 2 or more which is not yet support in the P-tile PCIe IP.
Hope this clear.
seanw_skhmsHi,
Let me ask the question in other way. In the example design you sent me, the P-Tile is configured to the 4X4 RP mode, and on the AVMM bus connection side the jtag-avmm bridge is connected to drive the P0 core only. The question is that when user drives the P0 core through jtag to create a PCIe transaction, the PCIe transaction will show up on which X4 lanes group? on the lane#0-3 or lane#4-7 or others?
Thanks,
Xiao
