Forum Discussion
Occasional ContributorWhy does Agilex-F PCIe RP IP example design assign the P0 to PCIe lane#0-3 instead of lane#4-7 ?
Ok after understanding further by checking the ED Qsys (platform designer).
I can see the JTAG master component is connecting to P0 of the P-tile IP. By right it should connect to channel 4-7 based on table 57. However, we not sure why ED connects it to 0-3, I will check this with the internal team but will need some time.
However, for urgent sake, you can try the approach by using lane 4-7 for the example design. If not working, then we will give a try on other port (by changing the connection in the Qsys) or another lane on assignment editor.
Frequent ContributorHi Sir,
The same document already stated there:
Port bifurcation for Gen3 x8, Gen4 x8 and Gen4 x4 will be available in a future release of Intel Quartus Prime.
It is not yet available for current quartus version.
I think you can try to change the location assignment and re-compile and see Quartus let you change it to lane#4-7.
Occasional ContributorI am using Quartus V20.2, and the P-Tile AVMM PCIe IP version 3.0.0. The IP generation tool GUI shows the options for using "Gen4X8/Gen4X8 EP" and "Gen4X4/Gen4X4/Gen4X4/Gen4X4 RP" configuration modes, which matches with the table-6 (also table-57) in UG-20237.
I have tried to use lane#4-7 in the "Gen4X4/Gen4X4/Gen4X4/Gen4X4 RP" configuration mode. Both of the synthesis and fit reports are showing expected connection without giving me any errors. But since the simulation is not supported for the 4x4 RP configuration in the current version of tool, it can only be verified in lab later.
regards,
Xiao
