Forum Discussion
Occasional ContributorWhy do i get this error when I use lvds?
Hello guys,
My device is 10CX220YF780E5G and the Quartus is QPP23.4. I implemented one channel LVDS receiver in my project. External PLL was checked. After full complilation, I found LVDS module was optimaized away. So I constrained LVDS output data to FPGA output pins. Then I got the following error. Can anyone tell me what blocks me to use lvds?
It seems that I violated some limitation of lvds application. However, I don't know what limitation I have violated.Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 38 pins of 45 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS_CLOCK_TREE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175020): The Fitter cannot place logic LVDS_CLOCK_TREE that is part of LVDS SERDES Intel FPGA IP LVDS_1Ch6B_RX_altera_lvds_2001_3ymtrna in region (38, 32) to (38, 32), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The LVDS_CLOCK_TREE name(s): u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below: Info (175013): The LVDS_CLOCK_TREE is constrained to the region (38, 32) to (38, 32) due to related logic Info (175015): The I/O pad clkin is constrained to the location PIN_AA18 due to: User Location Constraints (PIN_AA18) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 19 Info (14709): The constrained I/O pad drives a IOPLL, which drives this LVDS_CLOCK_TREE Error (175006): There is no routing connectivity between the LVDS_CLOCK_TREE and destination LVDS_CHANNEL Info (175027): Destination: LVDS_CHANNEL u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|channels[0].rx_non_dpa.serdes_dpa_inst~CHANNEL Info (175015): The I/O pad M10_TO_C10_LVDS_RX is constrained to the location PIN_P3 due to: User Location Constraints (PIN_P3) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 29 Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements Info (175021): The destination LVDS_CHANNEL was placed in location LVDS_CHANNEL containing P3 Info (175029): 2 locations affected Info (175029): LVDSCLOCKTREE_X38_Y32_N4 Info (175029): LVDSCLOCKTREE_X38_Y32_N5 Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. Error (16297): An error has occurred while trying to initialize the plan stage. Error: Quartus Prime Fitter was unsuccessful. 7 errors, 2 warnings Error: Peak virtual memory: 1397 megabytes Error: Processing ended: Mon Jul 29 17:45:25 2024 Error: Elapsed time: 00:00:09 Error: System process ID: 12428
Hi,
Yes, I found it in Volume 2, pages 4-18, from the link I provided earlier.
Let me know if you can't find it.
Regards,
Aqid
20 Replies
AqidAyman_AlteraRegular Contributor
Hello,
Can you try to change the pin assigned for the dedicated clock input to be in the same bank as the LVDS channel pin?
Kindly confirm back if this suggestion is working or not.
Thanks.
MinzhiWangHello Aqid,
Thanks for you reply this post.
This issue happened just as I made one simple project for LVDS test and trying. Now we try internal PLL, instead of external PLL, the LVDS function looks fine.
As you mentioned to try clock input, as following images, we already try this to receiver external ADC output.
However, here i have another question about LVDS need you help. Which is of LVDS constrain. We know that LVDS needs input termination and with the value of "Differential", as above image. We applied this constrain for ADC output pairs. They run well.
So we have another type LVDS pairs input, which are not from external ADC chips. They come from comparator devices output. FPGA use differential I/O pairs to receiver them. When we apply same constrain as ADC output pairs, they can't run well. The comparator output run as pulse signal, we can use Signaltap to monitor its signal quality. It's very bad under this constrain.
But they can run well when On-Chip Termination for Transceiver Rx pin (with 100 ohms value)constrains were applied to them. My question is what's the different between them?
- AqidAyman_Altera
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