Why can't I compile an LVDS TX SERDES design in an Arria 10AX066 when I change the tx_outclk phase with values other then 0,180,360,...

I get these error messages when I put the phase for example to 90:

Error (129029): Input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LVDSFCLK_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

Info (129030): Output port LVDS_CLK of a twentynm_iopll primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_TOP_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_BOT_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Error (129029): Input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LOADEN_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

Info (129030): Output port LOADEN of a twentynm_iopll primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LOADEN_TOP_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LOADEN_BOT_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lane0:0:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Error (129029): Input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LVDSFCLK_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

Info (129030): Output port LVDS_CLK of a twentynm_iopll primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_TOP_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_BOT_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Error (129029): Input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LOADEN_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

Info (129030): Output port LOADEN of a twentynm_iopll primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LOADEN_TOP_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LOADEN_BOT_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:1:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Error (129029): Input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LVDSFCLK_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

Info (129030): Output port LVDS_CLK of a twentynm_iopll primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_TOP_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Info (129030): Output port LVDSFCLK_BOT_OUT of a twentynm_lvds_clock_tree primitive is a valid source for input port LVDSFCLK_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree"

Error (129029): Input port LOADEN_IN on atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree", which is a twentynm_lvds_clock_tree primitive, is not connected to a valid source

Info (129005): Input port LOADEN_IN of the atom "lvds_out:\g_lvds_out:g_lvds_out_lanes123:2:i_lvds_out|lvds_out_altera_lvds_171_xojisai:lvds_0|lvds_out_altera_lvds_core20_171_pxhn52y:core|altera_lvds_core20:arch_inst|phase_shifted_tx_outclock_serdes.outclock_tree" is not connected

I also get these messages on other clocks!

Can you share the link to which document you're referring to? Hope you've instantiated the LVDS IP as a component in the design and not as the top-level design itself.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

It's indeed instantiated as a component!

See page 19!

Hi ,

From the Error Message description the LVDS IP is not connected as per the guidelines. Requesting to check the design.

Regards,

RS​

Hi,

It does compile correctly when I put the phase to 0 or 180 or 360...

But not for 45, 90, 135....

So I assume that I connected the IP correctly?

Or is there a difference when using these phases?

Best regards,

Bruno.

Here is a bit of my VHDL:

i_lvds_ref_clk_pll: lvds_ref_clk_pll

port map (

refclk => i_lvds_ref_clk,

lvds_clk => lvdsPllFastClk,

loaden => lvdsPllLoadEna,

outclk_4 => lvdsPllPxlClk,

locked => lvdsPllLock,

rst => pllReset

);

-------------------------------------------------------------------------------

-- LVDS interfacing

-------------------------------------------------------------------------------

process(lvdsPxlClk, reset)

begin

if reset = '1' then

lvdsData <= (others=>(others=>'0'));

elsif rising_Edge(lvdsPxlClk) then

if lvdsData(0)(0) = '0' then

lvdsData <= (others=>(others=>'1'));

else

lvdsData <= (others=>(others=>'0'));

end if;

end if;

end process;

g_lvds_out: for i in 1 to c_lvdsLanes-1 generate

i_lvds_out : lvds_out

port map (

ext_coreclock => lvdsPllPxlClk,

ext_fclk => lvdsPllFastClk(1),

ext_loaden => lvdsPllLoadEna(1),

tx_coreclock => lvdsPxlCLk,

tx_in => lvdsData(i),

tx_out => o_lvds_data(((i+1)*11)-1 downto i*11),

tx_outclock => o_lvds_clk(i),

pll_areset => lvdsOutReset

);

end generate;

Hi ,

With my knowledge no, can you test as stand alone the IP project and check.

Regards,

RS​

Hi ,

Requesting to check a standalone PLL and check the standalone PLL is working fine.

Regards,

Rs​