Altera_ForumHonored Contributor12 years agoWhich pin is PLL1_CLKOUTp in EP4CE15F256? Hi, I managed to take advantage of the ATLPLL in EP4CE15F256. I think I should assign the clock output pin to a dedicated single-ended pin named "PLL1_CLKOUTp", for outputting a reference clo...Show More
Recent DiscussionsAgilex 3 PLL in Source Synchronous mode ?writing a word to cfm1 using on chip flash ip on max10MAX10 FPGA IOs not entering Tri-state (Hi-Z)To INTEL - Request for Compliance Data from your customerPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices