Forum Discussion
HuaYuLiang
New Contributor
4 years agoThanks your reply!
I can't understand "we do not provide the pin map", why??
AqidAyman_Altera
Regular Contributor
4 years agoHi YuLiang,
I apologize I do not have the answer for that. Instead, we provide the pin list for 10M02SCE144 as attached.
In the Intel® MAX® 10 FPGA Design Guidelines, it mentioned the usage of Quartus Prime Pin Planner for I/O pin planning. You can refer to the below links:
1.6.1.2. Use the Intel® Quartus® Prime Pin Planner for I/O pin...