Honored Contributor
Honored ContributorHello,
the GXB refclk input is different from regular Stratix LVDS receivers, I think. According to the manual, it's AC coupled and isn't intended for operation below the minimum PLL input frequency of 50 MHz. I assume that you selected LVDS as I/O standard for the refclk input? A wrong termination could be normally seen from the input level at the differential pins, with missing termination, the input signal would be to high but still almost symmetrical and the receiver probably operational at lower (< 100 MHz) frequency, perhaps with irregular timing. But it could be, that the RREFB derived reference current has other uses inside the GXB block, may be also for the differential clock receivers. Regards, Frank
ContributorHi Frank,
Your answer helps. Recently I am really struggling with this Calibration thing. From your words, "recalibration is required to fine tune the internal parameters of the TX PLL, RX PMA and TX PMA to ensure that they are optimal at your new data rates. This is also to ensure that XCVR blocks will operate as expected at the new data rates", can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?
If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.
https://forums.intel.com/s/question/0D50P00004Gf0dgSAB/what-would-happen-if-transceiver-calibration-fails
Thanks, and happy weekend.
