Forum Discussion
Altera_Forum
Honored Contributor
18 years agoFirstly, thanks a lot for FvM's help.
Here I have anothers question. The refclk of GXB is fed by the output of the EPLL5 with the I/O standard LVDS (device EP2s30),that is the output of the device is fed to its input. And the clock becomes deformed after the LVDS receiver,just like the output of the sinusoid clock through the waveform shaping circuit, and the duty cycle of the clock increases with the frequency.When the frequency of the refclk is more than 20MHz, the output of the LVDS reveiver is just a high level.Do you think this phenomenon is correlated with the absence of rref resistance, or for other reasons? By the way, the clock is ok before the LVDS receiver that I had measured.