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Altera_Forum's avatar
Altera_Forum
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12 years ago

What to do about excessive internal FPGA clock skew?

Hello,

I'm using the Triple Speed Ethernet core and when I run TimeQuest I get the following timing constraints error.

The timing requirements are not met by only a small margin but what got my attention is the rather high clock skew of 5 ns on the data arrival path:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8123

This is how the clock path looks like:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8122

Now it looks like that the clock mux is not using the dedicated clock routing network. What have I to do so that a clock mux instead of normal combinatorial logic gets instantiated?

Currently my clock mux looks like this in VHDL: 


  tx_clk_to_the_tse_mac <= enet_clk_125mhz when('1' = eth_mode_from_the_tse_mac) else -- GbE Mode = 125MHz clock
                   enet_clk_2p5mhz when('1' = ena_10_from_the_tse_mac) else   -- 10Mb Mode = 2.5MHz clock
                   enet_clk_25mhz;                                    -- 100Mb Mode = 25MHz clock

Regards

Martin

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I'm using the following optimized version now, which helped to reduce the clock jitter because the clock signal is routed on dedicated clock nets now:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8198

    The clock mux is implemented like this now: 

      blk_enet_clkctrl: block
    signal
      enet_clkctrl_cs
        : std_logic_vector(1 downto 0) := (others => '0');
  begin
    enet_clkctrl_cs <= "10" when ('1' = eth_mode_from_the_tse_mac) else
      "11" when ('1' = ena_10_from_the_tse_mac) else
      "00";
    inst_enet_clkctrl: component enet_clkctrl
      PORT MAP
      (
        clkselect	=> enet_clkctrl_cs,
        inclk0x		=> CLKIN_25MHZ,
        inclk1x		=> '0',
        inclk2x		=> enet_clk_125mhz,
        inclk3x		=> enet_clk_2p5mhz,
        outclk		=> tx_clk_to_the_tse_mac
      );
    end block;